Pipelined processor designs typically incorporate master-slave processor configurations. The master processor issues an instruction to be performed by the slave processor. The instruction must therefore be transferred to the slave processor before it can be executed. The transfer of instructions from the master processor to the slave processor is complicated by traps and stalls which may occur in the master processor.
A problem occurs in a heavily pipelined master-slave processor system when the master processor issues an instruction to the slave processor before all of the exceptions i.e. traps, stalls, etc., that may affect the execution of the instruction are known to the master processor. This problem is encountered in a scalar-vector processor where vector instructions comprised of an opcode and a set of operands must be delivered from the scalar to the vector processor. The scalar or master processor tries to deliver both the command i.e. opcode, and the set of operands to the vector or slave processor for each vector instruction as quickly as possible. However, due to the fact that exceptions may occur during the scalar unit's fetching of the operands, the vector unit cannot begin to process the instruction.
One prior solution to the above problem has been to delay the issuing of the instruction from the master processor until the instruction is known to be free from exceptions. However, the performance of the system is degraded due to the delay introduced by having the vector processor perform the pre-decoding of the instruction only after the instruction has been completely transferred.
An alternative solution has been to allow the slave or vector processor to immediately begin executing the instruction. In order to function properly, the slave processor must therefore include complex trap and stall mechanisms. The trap and stall mechanisms are required in the slave processor in order to allow the instruction in progress to be aborted before any state of the slave processor is altered by the execution of the instruction.